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_______________general description the MAX530 is a low-power, 12-bit, voltage-output digi- tal-to-analog converter (dac) that uses single +5v or dual ?v supplies. this device has an on-chip voltage reference plus an output buffer amplifier. operating cur- rent is only 250? from a single +5v supply, making it ideal for portable and battery-powered applications. in addition, the ssop (shrink-small-outline-package) mea- sures only 0.1 square inches, using less board area than an 8-pin dip. 12-bit resolution is achieved through laser trimming of the dac, op amp, and reference. no further adjustments are necessary. internal gain-setting resistors can be used to define a dac output voltage range of 0v to +2.048v, 0v to +4.096v, or ?.048v. four-quadrant multiplication is pos- sible without the use of external resistors or op amps. the parallel logic inputs are double buffered and are compati- ble with 4-bit, 8-bit, and 16-bit microprocessors. for dacs with similar features but with a serial data interface, refer to the max531/max538/max539 data sheet. ________________________applications battery-powered data-conversion products minimum component-count analog systems digital offset/gain adjustment industrial process control arbitrary function generators automatic test equipment microprocessor-controlled calibration ____________________________features ? buffered voltage output ? internal 2.048v voltage reference ? operates from single +5v or dual ?v supplies ? low power consumption: 250? operating current 40? shutdown-mode current ? ssop package saves space ? relative accuracy: 1 / 2 lsb max over temperature ? guaranteed monotonic over temperature ? 4-quadrant multiplication with no external components ? power-on reset ? double-buffered parallel logic inputs ______________ordering information ordering information continued on last page. * dice are tested at t a = +25?, dc parameters only. MAX530 +5v, low-power, parallel-input, voltage-output, 12-bit dac ________________________________________________________________ maxim integrated products 1 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 d0/d8 v dd rofs rfb d4 d3/d11 d2/d10 d1/d9 top view vout v ss refout refgnd a0 d7 d6 d5 16 15 14 13 9 10 11 12 ldac clr agnd refin dgnd cs wr a1 dip/so/ssop MAX530 __________________pin configuration MAX530 refout refin rofs 2.048v reference power-on reset dac latch control logic refgnd agnd clr a0 a1 cs wr ldac v dd dgnd v ss vout rfb 17 14 nbl input latch d0/d8 d1/d9 d2/d10 d4 d3/d11 d6 d5 d7 nbm input latch nbh input latch 24 1 234567 21 20 23 12 19 18 13 22 15 8 9 11 10 16 12-bit dac latch ________________functional diagram call toll free 1-800-998-8800 for free samples or literature. part temp. range pin-package MAX530acng 0? to +70? 24 narrow plastic dip MAX530bcng 0? to +70? 24 narrow plastic dip MAX530acwg 0? to +70? 24 wide so MAX530bcwg 0? to +70? 24 wide so MAX530acag 0? to +70? 24 ssop MAX530bcag 0? to +70? 24 ssop MAX530bc/d 0? to +70? dice* ? ? 1 / 2 ? 1 / 2 ? 1 / 2 error (lsb) 19-0168; rev 3; 7/95
MAX530 +5v, low-power, parallel-input, voltage-output, 12-bit dac 2 _______________________________________________________________________________________ absolute maximum ratings v dd to dgnd and v dd to agnd ................................-0.3v, +6v v ss to dgnd and v ss to agnd .................................-6v, +0.3v v dd to v ss ............................................................... -0.3v, +12v agnd to dgnd........................................................-0.3v, +0.3v refgnd to agnd........................................-0.3v, (v dd + 0.3v) digital input voltage to dgnd ................... -0.3v, (v dd + 0.3v) refin .................................................(v ss - 0.3v), (v dd + 0.3v) refout .............................................(v ss - 0.3v), (v dd + 0.3v) refout to refgnd ................................... -0.3v, (v dd + 0.3v) rfb ...................................................(v ss - 0.3v), (v dd + 0.3v) rofs .................................................(v ss - 0.3v), (v dd + 0.3v) vout to agnd (note 1) .............................................. v ss, v dd continuous current, any input ........................................?0ma continuous power dissipation (t a = +70?) narrow plastic dip (derate 13.33mw/? above +70?) ......1067mw wide so (derate 11.76mw/? above +70?) .......... 941mw ssop (derate 8.00mw/? above +70?) ..................640mw operating temperature ranges: MAX530_c_ _ ...................................................0? to +70? MAX530_e_ _ ................................................-40? to +85? storage temperature range .............................-65? to +165? lead temperature (soldering, 10sec ) .......................... +300? stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: the output may be shorted to v dd , v ss , dgnd, or agnd if the continuous package power dissipation and current ratings are not exceeded. typical short-circuit currents are 20ma. electrical characteristics?ingle +5v supply (v dd = 5v ?0%, v ss = 0v, agnd = dgnd = refgnd = 0v, refin = 2.048v (external), rfb = rofs = vout, c refout = 33?, r l = 10k , c l = 100pf, t a = t min to t max , unless otherwise noted.) conditions bits 12 n resolution units min typ max symbol parameter v dd = 5v (note 2) ?.5 guaranteed monotonic lsb ? dnl differential nonlinearity lsb ? inl relative accuracy ppm/? 3 tcv os v dd = 5v unipolar offset temperature coefficient lsb 018 v os unipolar offset error ppm/? 1 gain-error temperature coefficient dac latch = all 1s, vout < v dd - 0.4v (note 2) lsb ? ge 4.5v v dd 5.5v (note 3) gain error (note 2) vout = 2v, load regulation ?lsb k 2 resistive load v 0v dd - 0.4 4.5v v dd 5.5v (note 3) output voltage range lsb/v 0.4 1 psrr gain-error power-supply rejection lsb/v 0.4 1 psrr unipolar offset-error power-supply rejection ma 20 i sc short-circuit current 0.2 dc output impedance v 0v dd - 2 reference input range code dependent (note 4) pf 10 50 reference input capacitance code dependent, minimum at code 555hex k 40 reference input resistance (note 5) db -80 ac feedthrough MAX530ac/ae MAX530bc/be MAX530_c/e MAX530_c/e static performance dac voltage output (vout) reference input (refin)
MAX530 +5v, low-power, parallel-input, voltage-output, 12-bit dac _______________________________________________________________________________________ 3 electrical characteristics?ingle +5v supply (continued) (v dd = 5v ?0%, v ss = 0v, agnd = dgnd = refgnd = 0v, refin = 2.048v (external), rfb = rofs = vout, c refout = 33?, r l = 10k , c l = 100pf, t a = t min to t max , unless otherwise noted.) parameter temperature coefficient symbol min typ max 30 units reference tolerance v refout ppm/? 2.013 2.083 dynamic performance v 2.017 2.079 reference output (refout) voltage output slew rate reference output resistance r refout 2 power-supply rejection ratio psrr 300 ?/v 0.15 0.25 v/? voltage output settling time noise voltage e n 400 25 ?p-p ? 30 50 digital feedthrough 5 nv-s 68 signal-to-noise plus distortion ratio sinad 68 db digital inputs (d0-d7, ldac , clr , cs , wr , a0, a1) logic high input v ih 2.4 v logic low input v il 0.8 v digital leakage current ? ? digital input capacitance 8 pf power supplies conditions MAX530be MAX530bc (note 8) 4.5v v dd 5.5v t a = +25? to ?.5lsb, vout = 2v MAX530ac/ae wr = v dd , digital inputs all 1s to all 0s unity gain (note 5) gain = 2 (note 5) v in = 0v or v dd 2.024 2.048 2.072 t a = +25? v dd = 5.0v 0.1hz to 10khz positive supply-voltage range v dd (note 6) 4.5 5.5 v positive supply current i dd outputs unloaded, all digital inputs = 0v or v dd 250 400 ? switching characteristics address to wr setup t aws 5 ns address to wr hold t awh 5 ns cs to wr setup t cws 0 ns cs to wr hold t cwh 0 ns data to wr setup t ds 45 ns data to wr hold t dh 0 ns wr pulse width t wr 45 ns ldac pulse width t ldac 45 ns clr pulse width t clr 45 ns internal power-on reset pulse width t por (note 4) 1.3 10 ? MAX530bc/be minimum required external capacitor c min 3.3 ?
electrical characteristics?ual ?v supplies (v dd = 5v ?0%, v ss = -5v ?0%, agnd = dgnd = refgnd = 0v, refin = 2.048v (external), rfb = rofs = vout, c refout = 33?, r l = 10k , c l = 100pf, t a = t min to t max , unless otherwise noted.) MAX530 +5v, low-power, parallel-input, voltage-output, 12-bit dac 4 _______________________________________________________________________________________ v dd = 5v, v ss = -5v MAX530ac/ae ?.5 MAX530bc/be MAX530_c/e guaranteed monotonic lsb ? dnl differential nonlinearity MAX530_c/e lsb ?.5 inl relative accuracy ppm/? conditions 3 tcv os v dd = 5v, v ss = -5v bipolar offset temperature coefficient lsb 08 v os bipolar offset error ppm/? 1 tc gain-error temperature coefficient lsb ? 4.5v v dd 5.5v -5.5v v ss -4.5v (note 3) gain error vout = 2v, load regulation ?lsb k 2 resistive load v v ss + 0.4 v dd - 0.4 4.5v v dd 5.5v, -5.5v v ss -4.5v (note 3) output voltage range lsb/v bits 12 n resolution 0.4 1 psrr gain-error power-supply rejection lsb/v 0.4 1 psrr bipolar offset-error power-supply rejection ma 20 i sc short-circuit current 0.2 dc output impedance v v ss + 2 v dd - 2 reference input range units min typ max symbol parameter code dependent (note 4) pf 10 50 reference input capacitance code dependent, minimum at code 555hex k 40 reference input resistance (note 5) db -80 ac feedthrough (note 7) v -5.5 -4.5 v ss negative supply voltage outputs unloaded, all digital inputs = 0v or v dd ? 150 200 i ss negative supply current outputs unloaded, all digital inputs = 0v or v dd ? 250 400 i dd positive supply current (note 6) v 4.5 5.5 v dd positive supply voltage static performance dac voltage output (vout) reference input (refin) reference output (refout) ?pecifications are identical to those under single +5v supply dynamic performance ?pecifications are identical to those under single +5v supply digital inputs (d0-d7, ldac , clr , cs , wr , a0, a1) ?pecifications are identical to those under single +5v supply power supplies switching characteristics ?pecifications are identical to those under single +5v supply
MAX530 +5v, low-power, parallel-input, voltage-output, 12-bit dac _______________________________________________________________________________________ 5 0.25 -1.25 012 integral nonlinearity vs. digital input code (0?1) -1.00 MAX530-1 digital input code (decimal) integral nonlinearity (lsb) 8 -0.50 2610 0 4 dual supplies single supply integral nonlinearity vs. digital input code (11?095) 11 512 1024 1536 2048 2560 3072 3584 4095 - 0.25 0 0.25 integral nonlinearity (lsb) digital input code (decimal) -110 0 1 10 1k 100k analog feedthrough vs. frequency -30 -70 max531-5 frequency (hz) analog feedthrough (db) 100 10k 1m -100 -90 -80 -60 -50 -40 -20 -10 refin = 2v p-p code = all 0s, dual supplies (?v) 2.055 2.045 -60 120 reference voltage vs. temperature max531-6 temperature ( c) reference voltage (v) 60 2.050 -20 20 80 100 40 0 -40 140 __________________________________________typical operating characteristics (t a = +25?, single supply (+5v), unity gain, code = all 1s, unless otherwise noted). 12 0 0 0.8 output sink capability vs. output pull-down voltage 2 10 max531-3 output pull-down voltage (v) output sink capability (ma) 0.6 6 4 0.2 0.4 8 1.0 14 16 6 0 04 output source capability vs. output pull-up voltage 1 5 max531-4 output pull-up voltage (v) output source capability (ma) 3 3 2 12 4 5 7 8 note 2: in single supply, inl and ge are calculated from code 11 to code 4095. note 3: zero code, bipolar and gain error psrr are input referred specifications. in unity gain, the specification is 500?. in gain = 2 and bipolar modes, the specification is 1mv. note 4: guaranteed by design. note 5: refin = 1khz, 2.0vp-p. note 6: for specified performance, v dd = 5v ?0% is guaranteed by psrr tests. note 7: for specified performance, v ss = -5v ?0% is guaranteed by psrr tests. note 8: tested at i out = 100?. the reference can typically source up to 5ma (see typical operating characteristics ). electrical characteristics?ual ?v supplies (continued) (v dd = 5v ?0%, v ss = -5v ?0%, agnd = dgnd = refgnd = 0v, refin = 2.048v (external), rfb = rofs = vout, c refout = 33?, r l = 10k , c l = 100pf, t a = t min to t max , unless otherwise noted.)
MAX530 +5v, low-power, parallel-input, voltage-output, 12-bit dac 6 _______________________________________________________________________________________ ____________________________typical operating characteristics (continued) (t a = +25?, single supply (+5v), unity gain, code = all 1s, unless otherwise noted). 0 0 500 supply current vs. refin 50 250 refin (mv) supply current ( m a) 300 150 100 100 200 400 200 50 150 250 350 450 refin = external refgnd = agnd refgnd = v dd MAX530-14 2.0480 2.0450 0 5.0 reference output voltage vs. reference load current 2.0455 2.0475 MAX530-15 reference load current (ma) reference output (v) 3.0 2.0465 2.0460 1.0 2.0 4.0 2.0470 0.5 1.5 2.5 3.5 4.5 a: digital inputs rising edge, b: vout , no load, 1v/div dual supply (?v) ldac = low bipolar configuration v refin = 2v a b settling time (rising) 5 m s/div -200 -300 1 gain and phase vs. frequency -100 -100 frequency (khz) gain (db) 10 100 0 -200 800 -180 0 180 gain phase (g = 2) (g = 1) phase shift (degrees) MAX530-10 a: digital inputs falling edge, 5v/div b: vout, no load, 1v/div dual supply (?v) ldac = low bipolar configuration v refin = 2v a settling time (falling) b 5?/div digital feedthrough a b a: d0...d7 = 100khz, 4vp-p b: vout, 10mv/div ldac = cs = high 2 m s/div 300 230 -60 -20 60 supply current vs. temperature 250 280 temperature (?) supply current ( m a) 20 100 260 290 270 240 -40 0 40 80 MAX530-7 4 -14 1 100 100k gain vs. frequency -12 max531-8 frequency (hz) gain (db) -8 -4 0 2 -2 -6 -10 1k 10k refin = 4vp-p dual supplies (?v) 80 0 10 1k 100k amplifier signal-to-noise ratio 10 max531-9 frequency (hz) signal-to-noise ratio (db) 20 40 60 30 50 70 10k 100 refin = 4vp-p dual supplies (?v)
MAX530 +5v, low-power, parallel-input, voltage-output, 12-bit dac _______________________________________________________________________________________ 7 ______________________________________________________________pin description * this applies to 4 + 4 + 4 input loading mode. see table 2 for 8 + 4 input loading mode. d0 (lsb) input dta when a0 = 0 and a1 = 1, or d8 input when a0 = a1= 1* d0/d8 24 positive power supply (+5v) v dd 23 offset resistor pin. connect to vout for g = 1, to agnd for g = 2, or to refin for bipolar output. rofs 22 feedback pin. op-amp feedback resistor. always connect to vout. rfb 21 voltage output. op-amp buffered dac output. vout 20 negative power supply. usually ground for single-supply or -5v for dual-supply operation. v ss 19 reference output. output of the internal 2.048v reference. tie to refin to drive the r-2r dac. refout 18 reference ground must be connected to agnd when using the internal reference. connect to v dd to disable the internal reference and save power. refgnd 17 load dac input (active low). driving this asynchronous input low transfers the contents of the input latch to the dac latch and updates vout. ldac 16 clear (active low). a low on clr resets the dac latches to all 0s. clr 15 analog ground agnd 14 reference input. input for the r-2r dac. connect an external reference to this pin or a jumper to refout (pin 18) to use the internal 2.048v reference. refin 13 digital ground dgnd 12 chip select (active low). enables addressing and writing to this chip from common bus lines. cs 11 write input (active low). used with cs to load data into the input latch selected by a0 and a1. wr 10 address line a1. set a0 = a1 = 0 for nbl and nbm, a0 = 0 and a1 = 1 for nbl, a0 = 1 and a1 = 0 for nbm, or a0 = a1 = 1 for nbh. see table 2 for complete input latch addressing. a1 9 address line a0. with a1, used to multiplex 4 of 12 data lines to load low (nbl), middle (nbm), and high (nbh) 4-bit nibbles. (12 bits can also be loaded as 8+4.) a0 8 d7 input dta, or tie to d3 and multiplex when a0 = 1 and a1 = 0* d7 7 d6 input dta, or tie to d2 and multiplex when a0 = 1 and a1 = 0* d6 6 d5 input dta, or tie to d1 and multiplex when a0 = 1 and a1 = 0* d5 5 d4 d3/ d11 d2/ d10 d1/ d9 name d4 input dta, or tie to d0 and multiplex when a0 = 1 and a1 = 0* 4 d3 input dta, when a0 = 0 and a1 = 1, or d11 (msb) input when a0 = a1 =1* 3 d2 input dta, when a0 = 0 and a1 = 1, or d10 input when a0 = a1 = 1* 2 d1 input dta, when a0 = 0 and a1 = 1, or d9 input when a0 = a1 = 1* 1 function pin
MAX530 ________________detailed description the MAX530 consists of a parallel-input logic interface, a 12-bit r-2r ladder, a reference, and an op amp. the functional diagram shows the control lines and signal flow through the input data latch to the dac latch, as well as the 2.048v reference and output op amp. total supply current is typically 250? with a single +5v supply. this circuit is ideal for battery-powered, microprocessor-con- trolled applications where high accuracy, no adjustments, and minimum component count are key requirements. r-2r ladder the MAX530 uses an ?nverted?r-2r ladder network with a bicmos op amp to convert 12-bit digital data to analog voltage levels. figure 1 shows a simplified diagram of the r-2r dac and op amp. unlike a standard dac, the MAX530 uses an ?nverted?ladder network. normally, the refin pin is the current output of a standard dac and would be connected to the summing junction, or virtual ground, of an op amp. in this standard dac configura- +5v, low-power, parallel-input, voltage-output, 12-bit dac 8 _______________________________________________________________________________________ 2r 2r 2r 2r 2r rrr msb output buffer vout rfb rofs MAX530 2r 2r refin agnd dac latch r = 80k w lsb nbl input latch nbh input latch nbm input latch d0/d8 d1/d9 d2/d10 d4 d3/d11 d6 d5 d7 2.048v refout refgnd *shown for all 1s * lsb msb clr figure 1. simplified MAX530 dac circuit tion, however, the output voltage would be the inverse of the reference voltage. the MAX530? topology makes the ladder output voltage the same polarity as the reference input, which makes the device suitable for single-supply operation. the bicmos op amp is then used to buffer, invert, or amplify the ladder signal. ladder resistors are nominally 80k to conserve power and are laser trimmed for gain and linearity. the input impedance at refin is code dependent. when the dac register is all 0s, all rungs of the ladder are grounded and refin is open or no load. maximum loading (mini- mum refin impedance) occurs at code 010101... or 555hex. minimum reference input impedance at this code is guaranteed to be not less than 40k . the refin and refout pins allow the user to choose between driving the r-2r ladder with the on-chip refer- ence or an external reference. refin may be below ana- log ground when using dual supplies. see the external reference and four-quadrant multiplication sections for more information. internal reference the on-chip reference is laser trimmed to generate 2.048v at refout. the output stage can source and sink current so refout can settle to the correct volt- age quickly in response to code-dependent loading changes. typically source current is 5ma and sink cur- rent is 100?. refout connects the internal reference to the r-2r dac ladder at refin. the r-2r ladder draws 50? maximum load current. if any other connection is made to refout, ensure that the total load current is less than 100? to avoid gain errors. a separate refgnd pin is provided to isolate refer- ence currents from other analog and digital ground currents. to achieve specified noise performance, con- nect a 33? capacitor from refout to refgnd (see figure 2). using smaller capacitance values increases noise, and values less than 3.3? may compromise the reference? stability. for applications requiring the low- est noise, insert a buffered rc filter between refout and refin. when using the internal reference, refgnd must be connected to agnd. in applications not requiring the internal reference, connect refgnd to v dd , which shuts down the reference and saves typ- ically 100? of v dd supply current.
output buffer the output amplifier uses a folded cascode input stage and a type ab output stage. large output devices with low series resistance allow the output to swing to ground in single-supply operation. the output buffer is unity-gain stable. input offset voltage and supply cur- rent are laser trimmed. settling time is 25? to 0.01% of final value. the output is short-circuit protected and can drive a 2k load with more than 100pf of load capacitance. the op amp may be placed in unity-gain (g = 1), in a gain of two (g = 2), or in a bipolar-output mode by using the rofs and rfb pins. these pins are used to define a dac output voltage range of 0v to +2.048v, 0v to +4.096v or ?.048v, by connecting rofs to vout, gnd, or refin. rfb is always con- nected to vout. table 1 summarizes rofs usage. external reference an external reference in the range (v ss + 2v) to (v dd - 2v) may be used with the MAX530 in dual-sup- ply, unity-gain operation. in single-supply, unity-gain operation, the reference must be positive and may not exceed (v dd - 2v). the reference voltage determines the dac? full-scale output. because of the code- dependent nature of reference input impedances, a high-quality, low-output-impedance amplifier (such as the max480 low-power, precision op amp) should be used to drive refin. if an upgrade to the internal reference is required, the 2.5v max873a is ideal: ?5mv initial accuracy, 7ppm/? (max) temperature coefficient. power-on reset an internal power-on reset (por) circuit forces the dac register to reset to all 0s when v dd is first applied. the por pulse is typically 1.3?; however, it may take 2ms for the internal reference to charge its large filter capacitor and settle to its trimmed value. in addition to por , a clear (clr ) pin, when held low, sets the dac register to all 0s. clr operates asynchro- nously and independently from chip select (cs ). with the dac input at all 0s, the op-amp output is at zero for unity-gain and g = 2 configurations, but it is at -v ref for the bipolar configuration. shutdown mode the MAX530 is designed for low power consumption. understanding the circuit allows power consumption management for maximum efficiency. in single-supply mode (v dd = +5v, v ss = gnd) the initial supply cur- rent is typically only 160?, including the reference, op amp, and dac. this low current occurs when the power-on reset circuit clears the dac to all 0s and forces the op-amp output to zero (unipolar mode only). see the supply current vs. refin graph in the typical operating characteristics . under this condition, there is no internal load on the reference (dac = 000hex, refin is open circuit) and the op amp operates at its minimum quiescent current. the clr signal resets the MAX530 to these same conditions and can be used to control a power-saving mode when the dac is not being used by the system. MAX530 +5v, low-power, parallel-input, voltage-output, 12-bit dac _______________________________________________________________________________________ 9 rofs connected to: dac output range op-amp gain vout 0v to 2.048v g = 1 agnd 0v to 4.096v g = 2 refin -2.048v to +2.048v bipolar note: assumes rfb = vout and refin = refout = 2.048v table 1. rofs usage figure 2. reference noise vs. frequency 300 50 1 10 100 100 max531-fig02 frequency (khz) reference noise (? rms ) 150 200 250 0 0.1 1000 total referernce noise r s refout c refout c s tek 7a22 c refout = 3.3 m f c refout = 47 m f single pole rolloff 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 reference noise (mvp-p)
an additional 110? of supply current can be saved when the internal reference is not used by connecting refgnd to v dd . a low on resistance n-channel fet, such as the 2n7002, can be used to turn off the internal reference to create a shutdown mode with minimum current drain (figure 3). when clr is high, the transis- tor pulls refgnd to agnd and the reference and dac operate normally. when clr goes low, refgnd is pulled up to v dd and the reference is shut down. at the same time, clr resets the dac register to all 0s, and the op-amp output goes to 0v for unity-gain and g = 2 modes. this reduces the total single-supply operating current from 250? (400? max) to typically 40? in shutdown mode. a small error voltage is added to the reference output by the reference current flowing through the n-channel pull-down transistor. the switch? on resistance should be less than 5 . a typical reference current of 100? would add 0.5mv to refout. since the reference cur- rent and on resistance increase with temperature, the overall temperature coefficient will degrade slightly. as data is loaded into the dac and the output moves above gnd, the op-amp quiescent current increases to its nominal value and the total operating current aver- ages 250?. using dual supplies (?v), the op amp is fully biased continuously, and the v dd supply current is more constant at 250?. the v ss current is typically 150?. the MAX530 logic inputs are compatible with ttl and cmos logic levels. however, to achieve the lowest power dissipation, drive the digital inputs with rail-to-rail cmos logic. with ttl logic levels, the power require- ment increases by a factor of approximately 2. MAX530 +5v, low-power, parallel-input, voltage-output, 12-bit dac 10 ______________________________________________________________________________________ MAX530 MAX530 12-bit dac latch nbl input latch nbh input latch nbm input latch d0/d8 d1/d9 d2/d10 d4 d3/d11 d6 d5 d7 power-on reset control logic dac a0 a1 cs wr ldac clr 33 m f 2.048v reference refout refin rofs rfb v out +5v v ss dgnd 2n7002 refgnd agnd v dd figure 3. low-current shutdown mode clr cs wr ldac a0 a1 data updated l x x x x x reset dac latches h h x h x x no operation h x h h x x no operation h l l h h h nbh (d8-d11) h l l h h l nbm (d4-d7) h l l h l h nbl (d0-d3) h h h l x x update dac only h l l x l l dac not updated h l l l h h nbh and update dac table 2. input latch addressing
MAX530 +5v, low-power, parallel-input, voltage-output, 12-bit dac ______________________________________________________________________________________ 11 v ih v il data bits (8-bit byte or 4-bit nibble) a0-a1 v il v ih address bus valid t awh t cws t wr t cwh t aws t ds t dh data bus valid note: timing measurement reference level is v ih + v il 2 t clr cs wr clr ldac t ldac figure 4. MAX530 write-cycle timing diagram parallel logic interface designed to interface with 4-bit, 8-bit, and 16-bit micro- processors (?s), the MAX530 uses 8 data pins and double-buffered logic inputs to load data as 4 + 4 + 4 or 8 + 4. the 12-bit dac latch is updated simultane- ously through the control signal ldac . signals a0, a1, wr , and cs select which input latches to update. the 12-bit data is broken down into nibbles (nb); nbl is the enable signal for the lowest 4 bits, nbm is the enable for the middle 4 bits, and nbh is the enable for the highest and most significant 4 bits. table 2 lists the address decoding scheme. refer to figure 4 for the MAX530 write-cycle timing diagram. figure 5 shows the circuit configuration for a 4-bit ? application. figure 6 shows the corresponding timing sequence. the 4 low bits (d0-d3) are connected in paral- lel to the other 4 bits (d4-d7) and then to the ? bus. address lines a0 and a1 enable the input data latches for the high, middle, or low data nibbles. the ? sends chip select (cs ) and write (wr ) signals to latch in each of three nibbles in three cycles when the data is valid. figure 7 shows a typical interface to an 8-bit or a 16-bit ?. connect 8 data bits from the data bus to pins d0-d7 on the MAX530. with ldac held high, the user can load nbh or nbl + nbm in any order. figure 8a shows the corresponding timing sequence. for fastest throughput, use figure 8b? sequence. address lines a0 and a1 are tied together and the dac is loaded in 2 cycles as 8 + 4. in this scheme, with ldac held low, the dac latch is transparent. always load nbl and nbm first, followed by nbh. ldac is asynchronous with respect to wr . if ldac is brought low before or at the same time wr goes high, ldac must remain low for at least 50ns to ensure the cor- rect data is latched. data is latched into dac registers on ldac ? rising edge.
MAX530 +5v, low-power, parallel-input, voltage-output, 12-bit dac 12 ______________________________________________________________________________________ a0 = 1, a1 = 1 nbh nbm nbl cs wr ldac a0 = 1, a1 = 0 a0 = 0, a1 = 1 dac update figure 6. 4-bit ? timing sequence a0 = a1 = 1 a0 = a1 = 0 dac update nbh nbl & nbm cs wr ldac figure 8a. 8-bit and 16-bit ? timing sequence using ldac figure 5. 4-bit ? interface data bus d0-d3 d0-d3 d0-d3 d4-d7 mc6800 from system reset 02 r/w clr wr cs ldac en decoder a0-a15 a13-a15 address bus a0, a1 a0, a1 d0-d3 MAX530 figure 7. 8-bit and 16-bit ? interface d0-d7 data bus d0-d7 d0-d7 mc6809 from system reset clr a0-a1 wr cs ldac e r/w a0-a15 a13-a15 a0 address bus en decoder MAX530
MAX530 +5v, low-power, parallel-input, voltage-output, 12-bit dac ______________________________________________________________________________________ 13 a0 = a1 = 0 a0 = a1 = 1 dac update nbh nbl & nbm cs wr ldac = 0 (dac latch is transparent) figure 8b. 8-bit and 16-bit ? timing sequence with ldac = 0 unipolar configuration the MAX530 is configured for a 0v to +2.048v unipolar output range by connecting rofs and rfb to vout (figure 9). the converter operates from either single or dual supplies in this configuration. see table 3 for the dac-latch contents (input) vs. the analog vout (output). in this range, 1lsb = refin (2 -12 ). a 0v to 4.096v unipolar output range is set up by con- necting rofs to agnd and rfb to vout (figure 10). table 4 shows the dac-latch contents vs. vout. the MAX530 operates from either single or dual supplies in this mode. in this range, 1lsb = (2)(refin)(2 -12 ) = (refin)(2 -11 ). 33? refin refout agnd dgnd refgnd v dd v ss rofs rfb vout v out 0v to -5v +5v g = 1 MAX530 33? refin refout agnd dgnd refgnd v dd v ss rofs rfb vout v out 0v to -5v +5v g = 2 MAX530 figure 9. unipolar configuration (0v to +2.048v output) figure 10. unipolar configuration (0v to +4.096v output)
MAX530 +5v, low-power, parallel-input, voltage-output, 12-bit dac 14 ______________________________________________________________________________________ input output 1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000 (v refin ) 4095 4096 (v refin ) 2049 4096 (v refin ) 2048 4096 (v refin ) 2047 4096 (v refin ) 1 4096 ov = +v refin /2 table 3. unipolar binary code table (0v to v refin output), gain = 1 input output 1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000 +2 (v refin ) 4095 4096 +2 (v refin ) 2049 4096 +2 (v refin ) 2048 4096 +2 (v refin ) 2047 4096 +2 (v refin ) 1 4096 ov = +v refin table 4. unipolar binary code table (0v to 2v refin output), gain = 2 input output 1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000 (+v refin ) 2047 2048 (+v refin ) 1 2048 (-v refin ) 1 2048 (-v refin ) 2047 2048 0v (-v refin ) 2048 2048 = -v refin table 5. bipolar (offset binary) code table (-v refin to +v refin output) bipolar configuration a -v refin to +v refin bipolar range is set up by con- necting rofs to refin and rfb to vout, and operat- ing from dual (?v) supplies (figure 11). table 5 shows the dac-latch contents (input) vs. vout (out- put). in this range, 1 lsb = refin (2 -11 ). four-quadrant multiplication the MAX530 can be used as a four-quadrant multiplier by connecting rofs to refin and rfb to vout and, using (1) an offset binary digital code, (2) bipolar power supplies, and (3) a bipolar analog input at refin within the range v ss + 2v to v dd - 2v, as shown in figure 12. in general, a 12-bit dac? output is (d)(v refin )(g), where ??is the gain (1 or 2) and ??is the binary rep- resentation of the digital input divided by 2 12 or 4,096. this formula is precise for unipolar operation. however, for bipolar, offset binary operation, the msb is really a polarity bit. no resolution is lost, because there is the same number of steps. the output voltage, however, has been shifted from a range of, for example, 0v to 4.096v (g = 2) to a range of -2.048v to +2.048v. keep in mind that when using the dac as a four-quad- rant multiplier, the scale is skewed. the negative full scale is -v refin , while the positive full scale is +v refin - 1lsb.
MAX530 +5v, low-power, parallel-input, voltage-output, 12-bit dac ______________________________________________________________________________________ 15 33? refin refout agnd dgnd refgnd rofs rfb vout v out -5v +5v MAX530 figure 11. bipolar configuration (-2.048v to +2.048v output) figure 12. four-quadrant multiplying circuit refgnd agnd dgnd refin v dd v ss rofs rfb vout v out -5v +5v refin MAX530 __________applications information single-supply linearity as with any amplifier, the MAX530? output op amp offset can be positive or negative. when the offset is positive, it is easily accounted for. however, when the offset is nega- tive, the output cannot follow linearly when there is no negative supply. in that case, the amplifier output (vout) remains at ground until the dac voltage is sufficient to overcome the offset and the output becomes positive. the resulting transfer function is shown in figure 13. normally, linearity is measured after allowing for zero error and gain error. since, in single-supply operation, the actual value of a negative offset is unknown, it can- not be accounted for during test. in the MAX530, linear- ity and gain error are measured from code 11 to code 4095 (see note 2 under electrical characteristics ). the output amplifier offset does not affect monotonicity, and these dacs are guaranteed monotonic starting with code zero. in dual-supply operation, linearity and gain error are measured from code 0 to 4095. power-supply bypassing and ground management best system performance is obtained with printed cir- cuit boards that use separate analog and digital ground planes. wire-wrap boards are not recommended. the two ground planes should be connected together at the low-impedance power-supply source. agnd and refgnd should be connected together, and then to dgnd at the chip. for single-supply appli- cations, connect v ss to agnd at the chip. the best ground connection may be achieved by connecting the agnd, refgnd, and dgnd pins together and connecting that point to the system analog ground plane. if dgnd is connected to the system digital ground, digital noise may get through to the dac? ana- log portion. bypass v dd (and v ss in dual-supply mode) with a 0.1? ceramic capacitor connected between v dd and agnd (and between v ss and agnd). mount the capacitors with short leads close to the device. ac considerations digital feedthrough high-speed data at any of the digital input pins may couple through the dac package and cause internal stray capacitance to appear as noise at the dac out- put, even though ldac and cs are held high (see typical operating characteristics ). this digital feedthrough is tested by holding ldac and cs high and toggling the data inputs from all 1s to all 0s. analog feedthrough because of internal stray capacitance, higher-frequen- cy analog input signals at refin may couple to the output, even when the input digital code is all 0s, as shown in the typical operating characteristics graph analog feedthrough vs. frequency. it is tested by set- ting clr to low (which sets the dac latches to all 0s) and sweeping refin.
_ordering information (continued) MAX530 +5v, low-power, parallel-input, voltage-output, 12-bit dac 1 2 3 4 123 45678 0 positive offset negative offset dac code (lsbs) output (lsbs) figure 13. single-supply dac transfer function transistor count: 913; substrate connected to v dd . ldac refgnd a0 d4 d3/d11 agnd 0.133" (3.378mm) 0.087" (2.210mm) d5 d6 d7 a1 dgnd cs refin wr refout v ss vout d2/d10 d1/d9 d0/d8 v dd rofs rfb clr ___________________chip topography maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 1995 maxim integrated products printed usa is a registered trademark of maxim integrated products. error (lsb) 1 / 2 ? 1 / 2 ? 1 / 2 ? 24 ssop -40? to +85? MAX530beag 24 ssop -40? to +85? MAX530aeag 24 wide so -40? to +85? MAX530bewg 24 wide so -40? to +85? MAX530aewg 24 narrow plastic dip -40? to +85? MAX530beng 24 narrow plastic dip -40? to +85? MAX530aeng pin-package temp. range part

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